Communications devices are being developed and introduced into an evolving communications landscape that includes an increasing number of network protocols. It is often desirable and necessary for the devices to support multiple protocols. To support existing and new protocols, devices may require some reconfigurable logic, particularly at the physical (PHY) layer. Most reconfigurable logic components, however, are not viable for the current demands being placed on communication devices.
PHY layer processing encompasses such computationally intensive operations as filtering, resampling, fast-Fourier transforming (FFT), channel estimation, despreading and error correction decoding. Traditionally, PHY layer processing is performed using general purpose processors or digital signal processors (DSP) or application specific integrated circuits (ASIC). General purpose processors and DSPs are inherently programmed for a variety of PHY processing tasks; however, as data rates of network protocols have increased, it has become difficult for these types of processors to meet speed requirements while maintaining power consumption goals. ASICs are also used to implement PHY layer requirements and maintain power consumption goals. ASICs, however, are not easily reconfigured for processing additional protocols.
The invention is now described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is generally indicated by the left-most digit(s) in the corresponding reference number.